Semiconductor Engineering

AI Agents For UVM Generation: Challenges And Opportunities

Tackling a composite challenge that combines multi-stage task planning, long-context work, environment interaction, and ...
Business Wire

Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
EDN

Hardware-assisted verification, from its dawn to SystemVerilog, UVM, and transactors

My [LR’s] first exposure to hardware emulation happened circa 1995 upon visiting a major processor firm in Austin, Texas. Its lab was jam-packed from floor to ceiling with monstrous hardware emulators ...
Electronic Design

Make the Move from Module-Based Mixed-Signal Verification to UVM

This file type includes high resolution graphics and schematics when applicable. This article discusses techniques used to achieve this transition, including proxy SystemVerilog interface task calls ...
EDN

Synopsys claims first complete SystemVerilog flow

SAN FRANCISCO — Top-tier EDA vendor Synopsys Inc. Monday (March 20) laid claim to being the first EDA vendor to provide a complete SystemVerilog flow, saying the language is now supported throughout ...
Design-Reuse

Mentor Graphics Adds Memory Models to Create Industry's First Complete UVM SystemVerilog Verification IP Library

WILSONVILLE, Ore., Feb. 29, 2016 – Mentor Graphics Corporation (NASDAQ: MENT) today announced availability of the first entirely native UVM SystemVerilog memory verification IP library for all ...
mccormick.northwestern.edu

COMP_ENG 387: Real-Time Digital Systems Design and Verification with FPGAs

**Graduate students interested in taking this course for Winter 2024 should enroll in COMP_ENG 495: Real-Time Digital Systems Design and Verification with FPGAs to get graduate credit. Class ...
Electronic Design

SystemVerilog Gains A Foothold In Verification

SystemVerilog marries a number of verification concepts, primarily in the areas of design, assertions, and testbench creation, that were previously embodied in separate and sometimes proprietary ...
Design-Reuse

Advanced Techniques for IP Design and Verification

As designs grow in size and complexity, the challenges associated with low power and the growing design and verification gap have created the need for a paradigm shift in the IP design and ...
Semiconductor Engineering

Open-Source Verification

Sorting out what is meant by open-source verification is not easy, but it leaves the door open to new approaches Ask different people what open-source verification means and you will get a host of ...